The present disclosure relates to semiconductor memory devices, and more particularly, to a semiconductor memory device in which the number of components is reduced while data destruction in a non-selected memory cell during data write operation is reduced.
In conventional static random access memory (SRAM) devices, the further miniaturization of transistors included in a memory cell would increase significant variations in transistor characteristics, disadvantageously leading to destruction of data stored by the memory cell during memory operation.
There is a technique of reducing or preventing data destruction during read operation in which bit lines are provided for write operation and read operation separately. There is also a technique of reducing or preventing data destruction in a non-selected memory cell during write operation in which data read from the non-selected memory cell is written back to the non-selected memory cell (restore or write-back technique) (see Japanese Patent Publication No. 2007-4888 and International Publication WO/2008/032549).
On the other hand, there is also a known technique of using a hierarchical bit line architecture in which a local bit line connected directly to a memory cell has a short line length, and a local sense amplifier (SA) circuit is provided for each local bit line (see Japanese Patent Publication No. 2000-207886 and K. Takeda, et al., “Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs,” Technical Digest of Technical Papers, 2010 Symposium on VLSI Circuits, pp. 101-102).
A local SA circuit provided in the conventional hierarchical bit line architecture includes 22 components for each bit line when the local SA circuit is of single end type (see Japanese Patent Publication No. 2000-207886), and eight components for each bit line when the local SA circuit is of cross-coupled type (see K. Takeda, et al.). The area overhead of the SRAM device is disadvantageously large.